1. Field of the Invention
The present invention relates to programmable logic integrated circuits, and more particularly, to techniques for capturing signals at output pins in a programmable logic integrated circuit.
2. Description of Related Art
Often referred to as the JTAG standard after the Joint Test Action Group that developed it, the JTAG standard provides boundary-scan testing and debugging of printed circuit boards (PCBs) and systems to solve physical access problems on PCBs caused by crowded assemblies. The JTAG standard also provides in-system programming (ISP) of flash memory and field programmable gate arrays (FPGAs).
Boundary scan is a methodology that allows the control and observation of the boundary pins of a JTAG compatible device via software control. Boundary scan provides in-circuit testing without in-circuit test equipment. Boundary-scan testing embeds test circuitry at the chip level to form a complete board-level test protocol.
A digital system on a board includes two or more integrated circuit chips connected together through board level interconnect lines. The interconnect lines can be tested to ensure that they are working properly using a JTAG sample instruction. According to the JTAG sample instruction, the board level interconnect lines are tested by scanning in a “0/1” test signal at a first one of the integrated circuit chips, transmitting the signal across the interconnect lines, and then sampling the test signal at one or more receiving chips on the same board.
Each of the receiving chips receives the test signal at a pin and transmits the signal to a boundary scan register through an input buffer. If one of the receiving chips does not capture the correct test signal value, the interconnect lines are not functioning properly, possibly because of an open circuit or short circuit on one of the interconnect lines. The JTAG sample instruction is not dependent on the type of input/output (IO) standard used at the IO pins of the receiving chip.
In a typical FPGA, an input buffer and an output buffer is coupled to each input/output (IO) pin. The IO pins can be programmed to function exclusively as input pins, exclusively as output pins, or as bidirectional pins during user mode. Thus, there are input buffers coupled to pins that are programmed to be used exclusively as output pins. These input buffers are not used during the user mode. Therefore, in the Stratix® II and Cyclone™ II FPGAs made by Altera Corporation of San Jose, Calif., these unused input buffers are turned off to save IO power. Because the input buffers for the programmed output pins are turned off, the receiving chip cannot capture interconnect test signals applied to the output pins during the JTAG test phase. As a result, the JTAG sample instruction fails.
Turning off the unused input buffers to save power causes a conflict between the driver and the receiver chips during the board level interconnect test, because the receiver is not able to capture the signal sent from the driver. This conflict makes it difficult to test the integrity of the board level interconnect. It may still be possible to test the board level interconnect, but such techniques typically increase the complexity and test time. It would therefore be desirable to provide efficient techniques for capturing board level signals on programmable logic integrated circuits during boundary scan that minimize power consumption.